Driverless Cars & Connected Devices

From mobile computing to driverless cars, from health devices to connected homes – semiconductor technology is at the heart of  innovation.

Verification and Validation

It is no secret that 70% of the cost of semiconductor design is V&V. Functional safety and security have become a massive challenge not just for design but also for V&V.

V & V Challenges

The recent bad press due to Meltdown and Spectre should be a wake up call for design and verification. We certainly need technologies such as simulation and emulation but they are inherently incomplete and inadequate for systematic verification & validation (V&V)  for those designs that need higher assurance & compliance with the ISO standards, or security for the connected world.

The Promise of Formal

Formal methods offer a complementary verification paradigm rooted in efficient and exhaustive bug hunting as well as in obtaining exhaustive proofs of correctness.  The proliferation of formal EDA tools is increasing with some estimating it to be a $100+ million industry.

Formal's Broken Promise

Despite prolferation of formal tools, it remains a niche technology, with no cohesive adoption and deployment. Range of complex reasons but mainly due to a lack of good training and scalable methodologies that allow the end user to maximise the full potential of the tools.

The Axiomise Mission

Axiomise wants to make formal verification mainstream, by offering the best-in-class training and methodologies proven to work in practice, backed up by consistent project support and strategic consulting with EDA partners.
Ashish Darbari presented a talk on Using Formal to Vaccinate RISC-V Designs Against Catastrophic Bugs.  in the RISC-V Global Forum 2020