The Power of Formal: From flops to billion gate designs

Jointly with SemiWiki

When: 22 August 2023, 09.00 PST/17.00 GMT/18.00 CET

Presenter: Dr Ashish Darbari

The art & science of verifying multi-million flip-flop designs

Formal verification constructs a mathematical proof to verify a design-under-test (DUT) against a requirement. The requirement itself can be expressed in multiple ways. Traditionally, formal methods have required PhDs in Mathematics and CS.

However, modern-day deployment of formal methods can be done with ease if supported by great methodology. At Axiomise, we have been deploying production-grade formal methodology using all the commercial tools in the market with great success.

This talk will provide insights from the practical deployment of formal and show how scalable formal methodology based on abstraction, bug-hunting and coverage can be used to accomplish functional verification for designs with few flip-flops to a design with billion gates. The talk does not make any assumption on prior knowledge in formal verification.

Who should attend?

Verification Engineers
Verification Managers
Architects (CPU/GPU/System)
Practising verification professionals
Undergraduate students
Postgraduate students in CS, and EEE

What do you learn?

How to get started with abstraction in formal property checking?

Bug hunting and building proofs of bug absence

What is formal scenario coverage?

How to use coverage formal sign-off?