Dr. Ashish Darbari delves into the findings of the 2020 Wilson Research report with Harry Foster in the last podcast this year. Together we gain more insight into design and verification trends. With 68% projects running behind schedule, and an equal number requiring respin for IC/ASIC, is the industry doing enough? With 23% of the semiconductor designs using RISC-V; and the headcount ratio of verification to design being 5:1 for processor verification, perhaps it’s time to reflect and ask – are we doing enough?

With these thoughts, we sign-off 2020, wishing you all Happy holidays and merry Christmas.

We talk about hardware security this week. Tune in to bootstrap yourself with a primer on hardware security with Dr. Jason Oberg – CTO of Tortuga Logic. Jason is one of the best-known names in the industry in the field of hardware security.

Learn how to sign-off formal verification using six dimensions of coverage. Metric-driven verification is important, but we need to consider all aspects when using formal verification including qualitative and quantitative methods. We made it easy for you to use the six dimensions of coverage to sign-off RISC-V verification. Find out about it in more detail next week at the RISC-V summit.

Dr. Darbari talks about a new coverage solution for formal verification – scenario coverage. He describes why you need it, what it is, and how this has been used to verify the latest core from the OpenHW group – CVE4. Let’s cover our formal verification properly.

This week Dr. Darbari talks to Dr. Lucio Lanza – Managing Director of Lanza techVentures and the 2014 recipient of the Phil Kaufman Award for Distinguished Contributions to Electronic System Design. We talk about some of the exciting things Lucio did in his early days in Olivetti, Intel, Daisy Systems, and Cadence to his current engagement in pervasive healthcare. Previously, Dr. Lanza was a non-executive director of Arm, the world’s leading semiconductor IP company, and a member of the board of directors of Harris & Harris Group, an investor in transformative companies enabled by disruptive science. He currently serves as chairman of the board of PDF Solutions, Inc., a provider of technologies to improve semiconductor manufacturing yields, and is on the board of directors of several private companies.

Dr. Darbari got together with Rajat Swarup – cyber-security expert and ex-Director of Information Security, Blackrock. We talk about computer security, its origins, its impact on software, hardware secuirty and the role of formal methods. We ask Rajat about simple ways of keeping us safe.

Do you always need a GPU for L4/L5 autonomous driving? This week, Dr. Darbari sat down with Khaled Maalej – Founder & CEO, VSORA, a provider of high-performance silicon intellectual property (IP) solutions for artificial intelligence, digital communications, and advanced driver-assistance systems (ADAS) applications based in France. Find out how VSORA’s unique solutions are powering the next generation of driverless cars. We talk about programmable DSP, performance, low-power, and verification of petaflop computers on wheels.

In this podcast, Dr. Darbari discusses architectural formal verification and deadlocks in processors. Deadlocks can cause all sorts of issues in the design and though you may believe that reset would be a great way of bringing the chip out of the deadlock, your customers may not want to always reboot the device. Use Axiomise formalISA to find & fix deadlocks and if you like prove that they have been fixed.

This week, Dr. Darbari talks to Michiel Ligthart. Discover Michiel’s interesting journey from the Netherlands to the USA and find out how he ended being the president and chief operating officer of Verific Design Automation – one of the most well-known names in the EDA industry. We talk about the impact Verific is making in the design of several EDA tools including one of our favorite formal tools that uses Verific to compile 1.1 billion gate designs for functional formal verification in under an hour.

In this week’s podcast, Dr. Darbari talks to Professor Alastair Donaldson. He talks about a range of topics in software verification and describes how he went from being a keen musician to being a professor in computer science at Imperial College, London and a software engineer at Google. We talk about formal verification, metamorphic testing, concurrency, compilers, OpenCL, OpenGL, compiler bugs, the semantics of programming languages, SMT solvers, Z3, and as Alastair points out everything that is focussed on software correctness, performance, and portability. We also discuss computer science education at Imperial College.

Dr. Darbari demystifies the topic of architectural formal verification with the focus on RISC-V. He describes the similarities with simulation-based compliance testing and key benefits of using formalISA and formal verification for architectural compliance. A brand-new blog on this topic is available from Tech Design Forums.

In this podcast, Dr. Ashish Darbari talks to Steve Hoover, founder & CEO of Redwood EDA. Steve explains why he left a well-paid job at Intel to start Redwood EDA. Ashish asks Steve about why he has another language. The chat dives deep into Transactional-level Verilog (TL-Verilog), and why we should care about it? Steve explains how TL-Verilog will be a game-changer for RISC-V, formal methods, abstraction, UVM, tools, better debug, and open-source silicon efforts. Steve explains how his course is changing the way students learn digital design, computer architecture, and processor design. Do not forget to listen to Steve’s five tips.

The new course registration deadline is 24 August. Register at: https://www.vlsisystemdesign.com/riscv-based-myth/

In this week’s podcast, Dr. Darbari talks to Ted Miracco, CEO of Cylynt. Ted explains how he founded Cylynt, why it is called Cylynt, and what is the differentiation of its products. Find out how Cylynt technology is preventing software piracy and if you’re a software company you may want to look at this product!

In this podcast, Dr. Darbari talks to Bipul Talukdar from SmartDV. Bipul tells us that SmartDV has the largest portfolio of VIPs in the industry and he explans why this is so? Find out, how Bipul made his journey from Assam in India to leading a cutting-edge application engineering team at Smart DV?

Dr. Darbari talks to Matt Venn from Symbiotic EDA. Matt is working with Symbiotic EDA, promoting the use of Open Source Formal Verification tools in the IC and FPGA industries. Matt explains how Symbiotic EDA plans to disrupt the established market of formal methods by providing formal tools at a price that all can afford. Matt believes that Symbiotic EDA is incorporating new advanced technology in their tools and they provide an open-source version of their tools that gets used a lot amongst the research community. Find out why Matt believes this open-source model will give Symbiotic EDA an edge in the commercial domain as well.

Dr. Darbari sat down with Kiran Vittal from Synopsys and asks him why does Synopsys care about formal methods? Kiran is a Senior Product Marketing Director in the Verification Group at Synopsys, with 25 years of experience in EDA and semiconductor design. Kiran outlines that Synopsys is seeing massive traction for formal methods and the year-on-year growth in Synopsys for formal methods is clear evidence of this. When asked, how can budget companies afford formal tools from Synopsys, Kiran explains that Synopsys can also offer cost-effective solutions.

In this year’s DAC special, Dr. Darbari sat down with Joe Hupcey III from Mentor – a Siemens Business. Joe is a part of the Mentor’s Product Management team for Design & Verification Technologies; based in Mentor’s office in Silicon Valley, CA. He is responsible for the Questa Formal product line of automated applications and advanced property checking. Joe explains how from the days of 0-in acquisition Mentor has continued to invest in formal methods and now as part of Siemens, this investment is only growing. Despite selling simulation & emulation tools, Joe believes formal methods is one of the main technologies at Mentor being used in all shapes from apps to property checking.

In this year’s DAC special, Dr. Darbari sat down with Chris Komar, Product Engineering Group Director from Cadence Design Systems to find out what is hot with formal verification at Cadence, and why Cadence invests in formal methods? Chris emphasizes that formal is no longer “nice to have” but a “must-have”. Chris has been in EDA for the last 20 years focused on formal verification, starting with equivalence checking and has focused on formal property verification for the last 17 years.

In this DAC special, Dr. Darbari explains how Axiomise is making formal normal by combining training, and custom formal verification solutions. He talks about formalISA, a new app launched this week, and how it is able to obtain proofs, bugs, and coverage for establishing ISA compliance for RISC-V processors without writing a single line of verification code.

We are very excited to say that this week, Dr. Darbari is joined by Prof. Pascal Hitzler to discuss machine learning and formal methods. Prof. Hitzler is one of the rare few people in the world who works in the exciting field of neuro-symbolic learning and semantic web. We gain insights into what makes machine learning click, what neural network based deep learning is missing, and how rule-based reasoning grounded in formal methods can help.

This week, Dr. Darbari has a fireside chat with the super-guru of Portable Stimulus – Adnan Hamid, Founder & CEO of Breker Verification Systems. Adnan, a true global citizen, describes his personal journey and how he discovered working in the field of portable stimulus where Breker is producing revolutionary products.

In this podcast, Dr. Ashish Darbari outlines the ten reasons why formal verification should be used. Save money, find more bugs, find bugs quicker, prove bug absence, ship safe and secure chips.

In this week’s episode, Dr. Ashish Darbari talks to Simon Davidmann – Founder & CEO of Imperas. Simon talks about his journey from being an inquisitive child to becoming the CEO of Imperas. His many influences on our industry include Verilog, SystemVerilog, and the fascinating work being done at Imperas in creating simulators for multiple different processor families, including Arm, RISC-V, and MIPS. Thank you, Simon Davidmann, for taking the time out to talk to us.

 This week, Dr. Darbari has an informal chat about formal verification with Dr. Sean Safarpour – Group Director, Synopsys, and head of VC Formal product line. Sean talks about his journey from being a graduate student to leading a world-class team of engineers at Synopsys. Sean talks about tools, technology, methodology, coverage, and more.

What happens when you apply formal verification to find architectural flaws in processors? In this podcast, Dr. Ashish Darbari talks about an interesting way of using Axiomise ISA formal proof kit to find bugs in RISC-V cores. He describes how by using the combination of automated formal properties from the Axiomise proof kit together with constraints we can not only find bugs but also root-cause the precise nature of simulation resistant bugs. You might like this podcast if you ever wondered how constraints together with automated formal can be used to address the complex challenges of finding corner-case bugs in your CPU designs.

One of the biggest challenges with formal verification is scoping out what constraints are needed, and how they will be coded in formal verification for efficient predictable results. In this podcast, we discuss the role of constraints in formal verification.

Hope you liked last week’s podcast on formal coverage. Taking a different view this week, Dr. Darbari talks to Dr. Lauro Rizzatti – the emulation super Guru. Lauro traces his journey from Italy to the USA, explaining the many different, technological aspects of emulation, starting from its roots to the modern-day. Everyone in DV should find this highly educational.

In this podcast, Dr. Darbari talks about the role of coverage in formal verification and sign-off. We examine why coverage is important and what can be done to sign-off the verification with confidence. We discuss the interaction between structural coverage, functional coverage in simulation, and what happens for formal verification, and what should happen?

In this podcast, Dr. Darbari talks about the role of specifications in verification. Requirements & specifications play a very important part in establishing what can be obtained from a verification task. The general rule is if it ain’t specified it won’t be verified. After all, any testing & verification exercise needs to know what is being tested, and what is expected from a test?

In this podcast, Dr. Ashish Darbari talks to Harry Foster, Chief Scientist at Mentor Graphics about all things verification. Harry talks about ATPG, the origin of assertion languages, property checking, equivalence checking, and FPGAs. He shares insights about his association with Accellera and contributions to the Verification Academy. We talk about 5 tips that all verification engineers & managers will find useful to get productive with verification.

We describe what are the key factors to maximise verification ROI, focusing on Axiomise formal verification and how we can improve the return-on-investment.

Dr. Darbari talks about why processors need formal verification in the latest podcast. He describes why processors are complex, and why formal verification is a necessity.

In this podcast, we cover the rich history of formal methods, explaining the basics of formal verification covering theorem proving, model checking and equivalence checking. We explain why formal verification is perceived to be hard. We make formal verification easier!