Pleased to bring up the second part of the chat with Prof. Supratik Chakaraborty from IIT Bombay. We talk about boolean function synthesis, AI/ML, BDDs and SAT. Find out the next big thing in synthesis that has the potential to break the RSA!
Prof. Supratik Chakraborty is our guest this week. Tune in to find out how he came full circle from the corridors of IIT in his under-grad to being one of the top leaders in formal methods at IIT Bombay. In the first of the two-part podcast, Supratik talks to Dr Darbari about his passion for asynchronous circuits & formal methods, and word-level abstractions, and symbolic trajectory evaluation. Supratik shares his insights in teaching and research in formal methods and makes a strong case about why formal methods would be necessary for the design of machine learning hardware.
This week Dr. Darbari talks to Ravi Thummarukudy. Hear Ravi's fascinating story from growing up in a village in Kerala with no electricity to being a CEO of one of the top design IP companies Mobiveil Inc. From IIT Madras, and days at ISRO, Ravi describes how he moved on to make Mobiveil a trustworthy name in design IP using the mantra trust but verify.
This week we discuss our new formal verification course launched on 6 April, last week. If you're looking to understand how to apply formal methods, especially for industrial projects in VLSI, then we have something for you.
This week, Dr. Darbari talks to Dr. Daniel Zimmerman, Principal Researcher from Galois Inc. Lot of exciting conversation on formal methods and their applications to cryptography, homomorphic computing and Daniel also reveals the secret Ninja formal methods and the work done with Amazon on deploying software analysis.
This week Bob Smith is our guest. Bob is an executive director of the ESD Alliance, a SEMI Strategic Association Partner. He is responsible for the management and operations of the ESD Alliance, an international association of companies providing goods and services throughout the semiconductor design ecosystem.
How do we know when the proof is the valid proof? Can we always see the proof? Are visible proofs required for verification? Can you trust invisible proofs for sign-off? Welcome to formal verification! Tune in to this week's podcast to learn more.
In this episode, Dr. Darbari talks to a key leader in the field of the RISC-V ecosystem - Dr. Zvonimir Bandic - Senior director, Western Digital. Zvonimir traces his journey to the USA and describes the exciting field of storage, hard drives and cache-coherent interconnect. We talk about the CHIPS alliance, open-source, and how Western Digital is influencing the RISC-V ecosystem.
We demystify abstraction in today's podcast. Abstraction is the cornerstone of modern-day scalable formal verification. Classic papers in formal literature talk about abstraction as a Galois connection, but understanding abstraction when you're new to formal is not easy. We discuss it in detail in our upcoming webinar on 11 Feb 2021 but for now, here is an intuitive and simple explanation of abstraction and refinement.
We kick-off 2021 with our first podcast, talking to Calista Redmond, CEO of RISC-V International. Dr. Darbari asks Calista about the challenges and opportunities for the RISC-V revolution. Calista traces her roots from her days in IBM to what it takes to run an international organization spreading an open-source revolution in computer architecture like never seen before.
Dr. Ashish Darbari delves into the findings of the 2020 Wilson Research report with Harry Foster in the last podcast this year. With 68% projects running behind schedule, and an equal number requiring respin for IC/ASIC, is the industry doing enough? With 23% of the semiconductor designs using RISC-V; and the headcount ratio of verification to design being 5:1 for processor verification, perhaps it's time to reflect and ask - are we doing enough?
With these thoughts, we sign-off 2020, wishing you all Happy holidays and merry Christmas.
We talk about hardware security this week. Tune in to bootstrap yourself with a primer on hardware security with Dr. Jason Oberg - CTO of Tortuga Logic. Jason is one of the best-known names in the industry in the field of hardware security.
Learn how to sign-off formal verification using six dimensions of coverage. Metric-driven verification is important, but we need to consider all aspects when using formal verification including qualitative and quantitative methods. We made it easy for you to use the six dimensions of coverage to sign-off RISC-V verification. Find out about it in more detail next week at the RISC-V summit.
Dr. Darbari talks about a new coverage solution for formal verification - scenario coverage. He describes why you need it, what it is, and how this has been used to verify the latest core from the OpenHW group - CVE4. Let's cover our formal verification properly.
This week Dr. Darbari talks to Dr. Lucio Lanza - Managing Director of Lanza techVentures and the 2014 recipient of the Phil Kaufman Award for Distinguished Contributions to Electronic System Design. We talk about some of the exciting things Lucio did in his early days in Olivetti, Intel, Daisy Systems, and Cadence to his current engagement in pervasive healthcare.
Dr. Darbari got together with Rajat Swarup - cyber-security expert and ex-Director of Information Security, Blackrock. We talk about computer security, its origins, its impact on software, hardware secuirty and the role of formal methods. We ask Rajat about simple ways of keeping us safe.
Do you always need a GPU for L4/L5 autonomous driving? This week, Dr. Darbari sat down with Khaled Maalej - Founder & CEO, VSORA, a provider of high-performance silicon intellectual property (IP) solutions for artificial intelligence, digital communications and advanced driver-assistance systems (ADAS) applications based in France. Find out how VSORA's unique solutions are powering the next-generation of driverless cars. We talk about programmable DSP, performance, low-power and verification of peta-flop computers on wheels.
In this podcast, Dr. Darbari discusses architectural formal verification and deadlocks in processors. Deadlocks can cause all sorts of issues in the design and though you may believe that reset would be a great way of bringing the chip out of the deadlock, your customers may not want to always reboot the device. Use Axiomise formalISA to find & fix deadlocks and if you like prove that they have been fixed.
This week, Dr. Darbari talks to Michiel Ligthart. Discover Michiel's interesting journey from the Netherlands to the USA and find out how he ended being the president and chief operating officer of Verific Design Automation - one of the most well-known names in the EDA industry. We talk about the impact Verific is making in the design of several EDA tools including one of our favorite formal tools that uses Verific to compile 1.1 billion gate designs for functional formal verification in under an hour.
In this week's podcast, Dr. Darbari talks to Professor Alastair Donaldson. He talks about a range of topics in software verification and describes how he went from being a keen musician to being a professor in computer science at Imperial College, London, and a software engineer at Google.
Dr. Darbari demystifies the topic of architectural formal verification with the focus on RISC-V. He describes the similarities with simulation-based compliance testing and key benefits of using formalISA and formal verification for architectural compliance. A brand-new blog on this topic is available from Tech Design Forums.
In this podcast, Dr. Ashish Darbari talks to Steve Hoover, founder & CEO of Redwood EDA. Steve explains why he left a well-paid job at Intel to start Redwood EDA. Ashish asks Steve about why he has another language. The chat dives deep into Transactional Verilog (TL-Verilog), and why we should care about it?
In this week's podcast, Dr. Darbari talks to Ted Miracco, CEO of Cylynt. Ted explains how he founded Cylynt, why it is called Cylynt, and what is the differentiation of its products. Find out how Cylynt technology is preventing software piracy and if you're a software company you may want to look at this product!
In this podcast, Dr. Darbari talks to Bipul Talukdar from SmartDV. Bipul tells us that SmartDV has the largest portfolio of VIPs in the industry and he explans why this is so? Find out, how Bipul made his journey from Assam in India to leading a cutting-edge application engineering team at Smart DV?
Dr. Darbari talks to Matt Venn from Symbiotic EDA. Matt explains how Symbiotic EDA plans to disrupt the established market of formal methods by providing formal tools at a price that all can afford. Find out why Matt believes this open-source model will give Symbiotic EDA an edge in the commercial domain as well.
Dr. Darbari sat down with Kiran Vittal from Synopsys and asks him why does Synopsys care about formal methods? Kiran outlines that Synopsys is seeing massive traction for formal methods and the year-on-year growth in Synopsys for formal methods is clear evidence of this.
In this year's DAC special, Dr. Darbari sat down with Joe Hupcey III from Mentor – a Siemens Business. Joe explains how from the days of 0-in acquisition Mentor has continued to invest in formal methods and now as part of Siemens, this investment is only growing. Despite selling simulation & emulation tools, Joe believes formal methods is one of the main technologies at Mentor being used in all shapes from apps to property checking.
In this year's DAC special, Dr. Darbari sat down with Chris Komar, Product Engineering Group Director from Cadence Design Systems to find out what is hot with formal verification at Cadence, and why Cadence invests in formal methods? Chris emphasizes that formal is no longer “nice to have” but a “must-have”.
In this DAC special, Dr. Darbari explains how Axiomise is making formal normal by combining training, and custom formal verification solutions. He talks about formalISA, a new app launched this week, and how it is able to obtain proofs, bugs, and coverage for establishing ISA compliance for RISC-V processors without writing a single line of verification code.
We are very excited to say that this week, Dr. Darbari is joined by Prof. Pascal Hitzler to discuss machine learning and formal methods. Prof. Hitzler is one of the rare experts in the world who works in the exciting field of neuro-symbolic learning and the semantic web. We gain insights into what makes machine learning click, what neural network-based deep learning is missing, and how rule-based reasoning grounded in formal methods can help.
This week, Dr. Darbari has a fireside chat with the super-guru of Portable Stimulus - Adnan Hamid, Founder & CEO of Breker Verification Systems. Adnan, a true global citizen, describes his personal journey and how he discovered working in the field of portable stimulus where Breker is producing revolutionary products.
In this week's episode, Dr. Ashish Darbari talks to Simon Davidmann - Founder & CEO of Imperas. Simon talks about his journey from being an inquisitive child to becoming the CEO of Imperas. His many influences on our industry include Verilog, SystemVerilog, and the fascinating work being done at Imperas in creating simulators for multiple different processor families, including Arm, RISC-V, and MIPS. Thank you, Simon Davidmann, for taking the time out to talk to us.
In this podcast, Dr. Darbari talks about the connection between constraints and coverage in formal verification. He discusses why the two topics are closely connected using the concepts of controllability and observability and why proof-core and COI coverage are not the best mechanisms to sign-off formal verification, especially for inconclusive proofs.
This week, Dr. Darbari has an informal chat about formal verification with Dr. Sean Safarpour - Group Director, Synopsys, and head of VC Formal product line. Sean talks about his journey from being a graduate student to leading a world-class team of engineers at Synopsys. Sean talks about tools, technology, methodology, coverage, and more.
What happens when you apply formal verification to find architectural flaws in processors? In this podcast, Dr. Ashish Darbari talks about an interesting way of using Axiomise ISA formal proof kit to find bugs in RISC-V cores.
One of the biggest challenges with formal verification is scoping out what constraints are needed, and how they will be coded in formal verification for efficient predictable results. In this podcast, we discuss the role of constraints in formal verification.
Dr. Darbari talks to Dr. Lauro Rizzatti - the emulation super Guru. Lauro traces his journey from Italy to the USA, explaining the many different, technological aspects of emulation, starting from its roots to the modern-day. Everyone in DV should find this highly educational.
In this podcast, Dr Darbari will talk about the role of coverage in formal verification and sign-off. We examine why coverage is important and what can be done to sign-off the verification with confidence. We discuss the interaction between structural coverage, functional coverage in simulation and what happens for formal verification, and what should happen?
In this podcast, Dr Darbari talks about the role of specifications in verification. Requirements & specifications play a very important part in establishing what can be obtained from a verification task. The general rule is if it ain't specified it won't be verified. After all, any testing & verification exercise needs to know what is being tested, and what is expected from a test?
In this podcast, Dr. Ashish Darbari talks to Harry Foster, Chief Scientist at Mentor Graphics about all things verification. Harry talks about ATPG, the origin of assertion languages, property checking, equivalence checking, and FPGAs. He shares insights about his association with Accellera and contributions to the Verification Academy. We talk about 5 tips that all verification engineers & managers will find useful to get productive with verification.
In this podcast, we cover the rich history of formal methods, explaining the basics of formal verification covering theorem proving, model checking and equivalence checking. We explain why formal verification is perceived to be hard. We make formal verification easier!
In this podcast, Dr Ashish Darbari talks about testing and formal verification for SoCs. He describes the basics of simulation-based-verification techniques such as constrained random verification, directed testing, emulation, and formal verification. Subscribe to our youtube channel and our newsletters at axiomise.com. Ping us at email@example.com with your suggestions, questions, and feedback.
In this podcast, Dr Ashish Darbari presents a 30,000 ft introduction to a system-on-chip (SoC) and the numerous test and verification challenges that affect the design of these ubiquitous components that almost everyone on the planet owns!
Axiomise has turned two! In this first podcast, Axiomise founder & CEO Dr Ashish Darbari talks about his passion for formal verification and the different challenges engineers face in adopting formal. Tune in to enjoy our regular formal bytes!