RISC-V Formal Verification for ISA Compliance

When: 7 July 2020, 18.00 British Summer Time

Presenter: Dr Ashish Darbari & Xiaolin Chen, Synopsys

Verify beyond doubt that your design works

RISC-V is an open standard instruction set architecture. It has experienced exponential growth in recent years, enabling users to design custom processors more quickly and cost effectively to meet today’s demand for more technological innovations in the CPU, GPU, AI, ML spaces.

However, verification of the processor to find all corner-case bugs from the architectural and microarchitectural levels pose a tremendous challenge for dynamic simulation and emulation. Formal verification is known for its ability to prove the absence of bugs as well as find those complex corner-case bugs.

In this webinar, we will present a solution powered by a unique combination of Synopsys VC Formal apps and Axiomise’s RISC-V ISA formal solution enabling fast corner-case bug hunting, and exhaustive proofs of bug absence obtaining ISA compliance for RISC-V.

Who should attend?

Verification Engineers
Verification Managers
Architects (CPU/GPU/System)
Practising verification professionals
Undergraduate students
Postgraduate students in CS, and EEE

What do you learn?

Why processors are complex? 
How to apply formal verification for the processors?

How to find bugs and exhaustively verify processors?