When: 27 April 2020, 1700-18.00 British Summer Time

Presenter: Dr. Ashish Darbari

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Verify beyond doubt that your design works

In this webinar, we will describe a process of verifying RISC-V processors using formal verification.

RISC-V processors have become the talk of the town. The RISC-V architecture is open-source encouraging a whole family of new developers to design RISC-V cores. Design of processors have truly become democratized, but what about validation and verification? How do we ensure that these processors work as intended? Can simulation alone ensure that these processors do not have any corner-case defects?

In this webinar, we will explore why formal verification is a necessity for verifying RISC-V designs, and how we can exploit formal methods to find corner-case bugs in pre-verified processors, already deployed in silicon. Anyone with an interest in processor design and verification will benefit from this webinar.