Welcome to the Axiomise Blog
At Axiomise, we’re passionate about advancing the frontiers of formal verification. Our Tech Blog is where innovation meets insight, a dedicated space where our engineers, researchers, and thought leaders share deep dives into formal methods, real-world verification challenges, cutting-edge tools, and lessons learned from the field.
Whether you’re an industry expert, a verification engineer, or simply curious about the power of formal, this blog is your window into the minds shaping the future of semiconductor design verification. Expect hands-on tutorials, expert commentary, project highlights, and the latest updates from the formal ecosystem.
Explore. Learn. Challenge the status quo, formally.
Technical Articles
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Why Your NoC Verification Strategy Must Use Formal
This article shows why traditional simulation cannot safely verify modern coherent network‑on‑chip (NoC) fabrics, and how subtle corner‑case bugs can cause deadlocks and silent data corruption in AI and high‑performance SoCs. It explains how exhaustive formal verification, and specifically Axiomise’s nocProve app, can mathematically prove bug absence or uncover hidden NoC vulnerabilities before tape‑out.
Hidden underflow in a BF16 divider
DVCon USA revealed that formal verification is already handling billion-gate designs—but the real challenge is not tools, but methodology and how effectively it is applied in real-world verification flows.
11 Questions about Formal Verification
DVCon USA revealed that formal verification is already handling billion-gate designs—but the real challenge is not tools, but methodology and how effectively it is applied in real-world verification flows.
Becoming ADEPT in Formal Verification
The ADEPT FV flow applies formal verification across the entire design lifecycle—Avoid, Detect, Erase, and Prove—to catch bugs early, strengthen correctness, and build continuous coverage, enabling more robust, scalable, and predictable tape-out.
Exhaustive Formal Verification of Packet Based Designs
Serial packet-based designs are difficult to verify due to deep state dependencies and history-sensitive behavior. By using abstraction techniques such as smart tracking and assume-guarantee reasoning, verification becomes scalable while still ensuring correct packet ordering and significantly improving proof convergence.
Living life in the Formal Lane with Confidence
Despite its proven value, formal verification remains underused due to gaps in training, methodology, processes, and consistent application across projects. Making formal mainstream requires a systematic approach, the right expertise, and continuous support to deliver more reliable, bug-free designs at scale.
Ten Rules to Successfully Deploy Formal
Formal verification success is not driven by expertise alone, but by methodology and disciplined execution. Focusing on requirements, prioritising effectively, combining formal with simulation, and using strong planning, coverage, and reviews makes it a practical and high-impact verification approach.
When ” Silicon Proven” Is Not Good Enough
From Meltdown to Spectre, hidden vulnerabilities exposed deep flaws in modern computing, showing that security is not just a software concern but a fundamental hardware challenge that must be addressed at design time to prevent costly failures.
My Journey into Formal Verification Explained
From a childhood surrounded by engineering in India to influencing formal verification at companies like Intel, ARM, and OneSpin, this journey reflects curiosity, persistence, and global impact. It mirrors the evolution of an entire field and shows why formal verification is now essential in modern technology.
Axiomise in the Industry
Articles and collaborations published with external industry platforms, highlighting Axiomise’s expertise in formal verification.
SemiEngineering
Observability Is A Missing Layer In AI-Era Chiplet Design
Axiomise and industry experts highlight that AI can only make silicon truly self‑aware and self‑managing when observability is built into the fabric, with standardized, secure telemetry across multi‑die and chiplet systems so behavior can be monitored, understood, and acted on at scale.
SemiEngineering
Rethinking Chip Verification
In this discussion, Ashish Darbari explains why the industry needs a more precise, machine-readable golden specificationto reduce ambiguity, prevent spec drift, and improve verification confidence across increasingly complex chip and chiplet designs.
SemiEngineering
I/O Design Challenges Grow In AI Data Centers And HPC Clusters
Axiomise highlights that in AI data centers and multi‑die systems, the toughest I/O challenges arise from the tight coupling of thermal, mechanical, and electrical effects across heterogeneous dies and packages, which current tools still struggle to handle in a unified way.
SemiEngineering
Swapping Out Chiplets: I/Os Vs. Compute
Axiomise and industry experts highlight that, in multi‑die designs, it is often best to reuse I/O chiplets on mature nodes while swapping out the compute die to gain performance and power improvements across generations.