Power, performance and area (PPA) is a significant challenge for designers and architects building any silicon. The problem is three-dimensional and complex to solve with precise certainty. Invariably, heavy use of simulation vectors is exercised to examine the relationship between these dimensions, but the analysis is non-exhaustive leaving room for errors. Verification engineers focus primarily on structural coverage to expose unreachable code in designs, mostly towards the tail end of the projects.

While structural coverage is useful to expose unreachable (deadcode) code, it cannot expose redundant, partial or under-utilised code. 

footprint™ allows an efficient and fast analysis for identifying redundant design components that provides a quick feedback loop to the architects and designers while they bring up a new design, allowing them to exhaustively analyse the wasted area while focussing on power and performance optimisations. footprint efficiency stems from making the analysis on a component level. The report generated from footprint is a component specific categorization.

footprint is part of the axiomiser® platform that offers a one-stop shop for all its apps.

1. Exhaustive analysis of entire designs powered by formal methods
2. Finds unused area in your silicon
3. Formal methods in the hands of designers, with no need to learn formal
4. Automated, Push-button, GUI-based interface
5. An agile and interactive user-centric interface that allows easy model refinement
6. Generates easy-to-read reports with zero noise
7. Goes beyond reachability analysis and structural coverage
8. Usable across the full continuum of the design cycle
9. Tested on 80+ designs, including CPUs, GPUs, communication IP, NoCs
10. Caught many design redundancy issues, causing PPA problems