RISC-V formal verification

Overview

Modern processors implement numerous optimizations for power, performance, and area. Optimizations such as pipelining, interlocking, and data forwarding introduce numerous data dependencies and hazards causing processors to deadlock or produce incorrect results. The number of instruction combinations, together with instruction interleaving and multiple register files and operands make it impossible for any simulation-based verification to be exhaustive.

Formal verification produces exhaustive proofs of correctness and finds corner-case bugs in design implementations. The challenges with formal verification, however, are:

  • Proof convergence is not guaranteed
  • No consistency of formal coverage models across different formal verification tools.
  • No consistency between formal coverage models and simulation

The formalISA® app addresses all these challenges successfully. Built on top of the first-generation ISA formal verification proof kit from Axiomise, the formalISA® app is powered by a clean graphical-user-interface that allows the end-user to push a few buttons to obtain formal verification results on a RISC-V core of their choice, using a formal verification tool of their choice.

The push-button ‘ Prove’ & ‘Cover’ solution eliminates the need to:

  • Write a single test case
  • Write complex test sequences
  • Write scoreboard or checkers
  • Write constraints
  • Randomize stimulus

Key Features of formalISA

  • Push-button, GUI based
  • Finds corner-case bugs in processor implementation for 32-bit and 64-bit processors
  • Support ready for RV21IMC, and RV64IMC instruction set
  • App tested on in-order cores as well as out-of-order cores
  • Builds mathematical proofs of bug absence for architectural and micro-architectural checks and covers
  • Intelligent Debug via i-RADAR saves time in debug and handover to designers
  • Scenario coverage generated automatically
  • Scheduler and Reporter for formal (SURF) provides all the essential summary in a dashboard
  • Vendor-neutral – use any formal verification tool of your choice
  • Visualize instruction-set behaviour using the scenario coverage solution
  • Predictable & Scalable run times
  • Establish ISA compliance via mathematical proofs

We have deployed our formalISA app in the field since last four years and found numerous bugs in previously verified processors as well as exhaustively proving bug absence. For details of our technology,  and the results, head to the RISC-V studio. This will show you the background technology.

RISC-V Studio

To see formalISA in action, head straight to the formalISA studio. Here you can see how the app is orchestrated to find bugs, and establish proofs. You will also see our cutting-edge intelligent debugger i-RADAR®, SURF, and ISA coverage analyzer® solution using scenario coverage.

formalISA Studio
RISC-V is a registered trademark of the RISC-V International.
Formal Proof Kit is a registered trademark of Axiomise Limited.
formalISA, i-RADAR, and ISA Coverage Analyzer are registered trademarks of Axiomise Limited.