​Mixed‑precision and transprecision floating‑point designs often reuse a wider internal datapath (FP32) to produce lower‑precision formats such as BF16 for AI/ML accelerators and other performance‑critical systems. This pattern can hide subtle bugs when correctness is judged only in the internal format.

In this case study, Axiomise engineers use floatrix to uncover an underflow bug in a BF16 divider from the fpnew FPU. Internally, the unit computes in FP32 and decides “no underflow, no inexact” for a tiny result. But once the same value is rounded into BF16, it becomes tiny + inexact, and under the RISC‑V BF16 rules underflow should be signalled. Because the flag logic is tied to FP32 rather than BF16, the design silently misses the required exception.

The article explains:

• Why mixed‑precision and transprecision FPUs are especially prone to format‑mismatch bugs.

• How shortcuts that reuse FP32 tininess and rounding logic for BF16 can violate architectural intent.

• How floatrix’s format‑aware formal models and SVA checkers expose hidden underflow and flag‑handling issues that simulation and traditional scoreboards fail to catch.

Read the full article on EDN

To dive into the detailed analysis, waveforms, and the broader family of related floating‑point bugs, read the full EDN article:

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This article was originally published by EDN. It is referenced here for informational purposes, with full acknowledgment and gratitude to EDN as the original publisher. Readers can access the complete article on the EDN website.