This article argues that AI’s real opportunity in EDA isn’t a smarter point tool, it’s coordinating the handoffs between tools, where most of the pain and lost intent actually live. Axiomise makes the case that AI-generated properties and assertions are hypotheses, not proof, and that the industry is shifting from ‘the simulation looked green’ to demanding machine-checkable evidence, use AI for speed, formal for truth.

This article argues that while LLMs can now draft formal properties from a specification, faster than any engineer could by hand, that speed creates a new risk: false confidence. Featuring Axiomise CEO Ashish Darbari, it makes the case that AI-generated properties are strong on syntax but weak on architectural intent, and that completeness can only be established by an engineer who understands the design’s intent, not by the AI itself.

This article argues that photonics turns chiplet design into a multi-physics co-design problem, where thermal, mechanical, and electromagnetic effects interact bidirectionally. Axiomise’s contribution highlights a verification asymmetry: the digital side of an electrical-optical boundary can be formally proven correct today, but the optical subsystem behind it can’t and argues that gap should worry system architects.

The final part of this three-way roundtable series looks at why the future of AI compute is heterogeneous, CPUs, GPUs, NPUs, optics, and custom accelerators working together, not one chip doing everything. Ashish Darbari argues that a cluster shifts the design problem from building one powerful machine to engineering a coordinated distributed system, where the communication hierarchy, from die-to-die links up through node fabrics to cluster-wide networking, shapes what the whole system can actually deliver.

This roundtable brings together experts from Arm, Axiomise, Cadence, Expedera, Siemens EDA, and Synopsys to unpack why compute clusters intensify rather than solve, the AI data center’s power problem. Axiomise argues that a cluster fundamentally changes the design problem: from building one powerful machine to engineering a coordinated distributed system, where correctness now depends on protocols, distributed state, and recovery semantics rather than local functional behavior alone.

This article argues that models in EDA and chip design must only be used within their intended, well-specified context, because every model is an approximation and misusing it can lead to costly errors. It emphasizes disciplined, traceable creation, tagging, and validation of both human- and AI-generated models, so teams can trust them in production while recognizing limits around accuracy, completeness, and training data.

This article explains why AI‑era, chiplet‑based systems need observability built into the fabric so telemetry can be collected and understood across dies and packages. It highlights that scalable, secure observability depends on standards, near‑sensor data reduction, and combining AI analytics with formal methods to pinpoint and prevent real failures.

This article argues that in AI data centers and HPC clusters, I/O connectors, protocols, and advanced packaging are now decisive design levers because data movement, reliability, and rack‑scale physics can bottleneck even the fastest chips. It shows how engineers must juggle airflow, cooling, multi‑die integration, redundancy, and congestion‑control protocols so clusters of GPUs and accelerators behave like a single, highly utilized compute system.

This article argues that in AI data centers and HPC clusters, I/O connectors, protocols, and advanced packaging are now decisive design levers because data movement, reliability, and rack‑scale physics can bottleneck even the fastest chips. It shows how engineers must juggle airflow, cooling, multi‑die integration, redundancy, and congestion‑control protocols so clusters of GPUs and accelerators behave like a single, highly utilized compute system.

This article argues that in AI data centers and HPC clusters, I/O connectors, protocols, and advanced packaging are now decisive design levers because data movement, reliability, and rack‑scale physics can bottleneck even the fastest chips. It shows how engineers must juggle airflow, cooling, multi‑die integration, redundancy, and congestion‑control protocols so clusters of GPUs and accelerators behave like a single, highly utilized compute system.

This article explains that AI and HPC chips now depend on several interconnect standards in one system, with each fabric (PCIe, CXL, UCIe, NVLink, UALink, Ultra Ethernet, emerging optical, etc.) chosen for a specific range, latency, and memory/compute role. It highlights that the real challenge is no longer finding a single “winner,” but cleanly combining multiple protocols without creating bugs or bottlenecks where they meet.