Formal Verification, Methodology & Best Practices, Tools, Solutions & Case Studies
Why Your NoC Verification Strategy Must Use Formal 4 min Read FollowFollowFollow Summary marketing@axiomise.com +44 1442 345046 This article shows why traditional simulation is not enough to verify modern coherent NoCs and how deep corner‑case bugs can silently cause...
Tools, Solutions & Case Studies
Hidden underflow in a BF16 divider 12 min Read FollowFollowFollow Summary marketing@axiomise.com +44 1442 345046 The article shows how a BF16 divider in a mixed‑precision FPU can silently miss underflow and inexact flags by judging results in internal FP32 instead of...
Industry Insights & Thought
11 Questions about Formal Verification 9 min Read FollowFollowFollow Summary marketing@axiomise.com +44 1442 345046 At DVCon USA, discussions highlighted that formal verification is already scaling to billion-gate designs, with methodology—not tool limits—being the...
Methodology & Best Practices
Becoming ADEPT in Formal Verification 16 min Read FollowFollowFollow Summary marketing@axiomise.com +44 1442 345046 The ADEPT FV flow uses formal verification throughout design—Avoid, Detect, Erase, and Prove—to catch bugs early, prove correctness, and build coverage...
Industry Insights & Thought
Living Life in the Formal Lane with Confidence 5 min Read FollowFollowFollow Summary marketing@axiomise.com +44 1442 345046 Despite its proven value, formal verification remains underused due to gaps in training, methodology, processes, and consistent application. To...
